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93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4615d 06h /minsoc/branches/verilator
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4616d 04h /minsoc/branches/verilator
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4616d 04h /minsoc/branches/verilator
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4616d 20h /minsoc/branches/verilator
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4616d 20h /minsoc/branches/verilator
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4616d 20h /minsoc/branches/verilator
87 Synchronizing scripts to behave exactly the same. rfajardo 4616d 21h /minsoc/branches/verilator
86 Updating configure script messages. rfajardo 4616d 22h /minsoc/branches/verilator
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4616d 22h /minsoc/branches/verilator
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v		 rfajardo 4617d 22h /minsoc/branches/verilator

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