URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator] - Rev 116

Rev	Log message	Author	Age	Path
96	Some files needed for Altera synthesis	javieralso	4615d 21h	/minsoc/branches/verilator
95	Makefile for Altera FPGAs fixed	javieralso	4617d 00h	/minsoc/branches/verilator
94	Fix bug in minsoc_top.prj for Altera synthesis	javieralso	4619d 09h	/minsoc/branches/verilator
93	Support for Altera synthesis. It needs some tune, but it works fine	javieralso	4619d 12h	/minsoc/branches/verilator
92	backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards.	rfajardo	4620d 10h	/minsoc/branches/verilator
91	prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found.	rfajardo	4620d 11h	/minsoc/branches/verilator
90	After minsoc_top.prj update, make regenerated src and xst files.	rfajardo	4621d 02h	/minsoc/branches/verilator
89	minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now.	rfajardo	4621d 02h	/minsoc/branches/verilator
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4621d 03h	/minsoc/branches/verilator
87	Synchronizing scripts to behave exactly the same.	rfajardo	4621d 04h	/minsoc/branches/verilator