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[/] [minsoc/] [branches] - Rev 136

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136 Installation on Ubuntu-11.10 has shown that a binary called makeinfo is required to install GDB. This binary can be installed on Ubuntu by installing the package texinfo. rfajardo 4556d 19h /minsoc/branches
134 run_sim.bat for ModelSim updated to acquire the firmware_size for command line input when running the testbench. rfajardo 4563d 23h /minsoc/branches
133 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

Applying Rubén Diez patch to avoid warnings on firmware load for simulation.		 rfajardo 4564d 00h /minsoc/branches
132 ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench. rfajardo 4567d 20h /minsoc/branches
131 Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. rfajardo 4567d 20h /minsoc/branches
130 minsoc_bench.v: task test_eth has to be phased out together with the ETHERNET definition. If there is no ETHERNET, test_eth cannot be defined. rfajardo 4567d 22h /minsoc/branches
129 Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready		 rfajardo 4568d 09h /minsoc/branches
128 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. rfajardo 4568d 10h /minsoc/branches
127 Removing redundant simulation output. rfajardo 4568d 16h /minsoc/branches
126 Updating information about simulation time for Ethernet test. rfajardo 4568d 16h /minsoc/branches
125 Adjusting testbench messages. Creating tasks for firmware tests. rfajardo 4568d 17h /minsoc/branches
124 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever. rfajardo 4568d 18h /minsoc/branches
123 Renaming reg final to firmware_size. Final is a keyword for Verilator. rfajardo 4568d 23h /minsoc/branches
122 Renaming minsoc-configure.sh to minsoc-setup.sh. rfajardo 4574d 13h /minsoc/branches
121 Asserting svn:executable properties of modelsim/*.bat scripts.

Including corrected patch for advanced debug system watchpoints under utils/setup. Configure script updated to use this instead of advanced debug system patches. This will remain so until the patch is corrected. The previous line still has the correct command.		 rfajardo 4574d 14h /minsoc/branches
120 ethmac.prj: a file was missing rfajardo 4574d 17h /minsoc/branches
119 Tricking Subversion to accept bat files that are now executable. rfajardo 4574d 18h /minsoc/branches
118 Configure scripts for Xilinx devices updated. All of them require to update or1200_defines.v. The non-standard part uses now the variable $BOARD to print that this board require non-standard update of files. rfajardo 4574d 18h /minsoc/branches
117 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead of GENERIC. rfajardo 4574d 18h /minsoc/branches
116 Configure scripts were trying to copy/patch projects files before creating them. Ordering is correct now. rfajardo 4574d 19h /minsoc/branches

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