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[/] [minsoc/] [tags/] [release-0.9/] [backend/] - Rev 141

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Rev Log message Author Age Path
42 Tagging release 0.9 of MinSoC. rfajardo 3550d 02h /minsoc/tags/release-0.9/backend/
40 Commiting a contributions directory, which has raw contributions of users. These contributions still have to be adapted to the system in order to work well. However, some users are certainly able to work with these versions.

FAQ: -added new idea to circumvent onboard DLC9 cable problem for adv_jtag_bridge
INSTALL: -gives a hint on how to install the system for Windows
HOWTO: -explains what a ucf file is and how to create it

backend: now we have the first contribution of a ucf file for the ML509 board (thanks to Matthew Hick)

Documentation: THESIS.txt explains to users, willing to tweak/understand the inner behavior of the OR1200 implementation of OpenRISC, what to read in order to get this information.
rfajardo 3556d 01h /minsoc/trunk/backend/
15 Including verified pinout for external spi flash on spartan3a dsp kit to its correspondent ucf constraint file. rfajardo 4038d 23h /minsoc/trunk/backend/
13 Updating spartan3e_starter_kit.ucf so that it does not deliver errors on mapping. Moreover it has been changed to off the shelf only have uart support. Ethernet support and generic JTAG can be added by uncommenting the corresponding lines. rfajardo 4048d 06h /minsoc/trunk/backend/
12 1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.
rfajardo 4050d 21h /minsoc/trunk/backend/
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4093d 05h /minsoc/trunk/backend/

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