URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench.v] - Rev 9

Rev	Log message	Author	Age	Path
9	Tiny change to testbench gain: -uart_srx is now reg for future testbench serial input to SoC.	rfajardo	5336d 03h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
8	Cosmetic changes to minsoc_bench.v: -reset and clock initialization are included into the main initial block, it had an own block before	rfajardo	5336d 03h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
4	minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary. jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it. Documentation now includes: -vpi module compilation -gdb patch for adv_jtag_bridge -ideas for future work on minsoc (To Do v.2)	rfajardo	5351d 09h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5355d 08h	/minsoc/tags/release-0.9/bench/verilog/minsoc_bench.v