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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [vpi/] - Rev 42

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42 Tagging release 0.9 of MinSoC. rfajardo 4952d 21h /minsoc/tags/release-0.9/bench/verilog/vpi/
4 minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.

jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.

Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2)
rfajardo 5492d 01h /minsoc/tags/release-0.9/bench/verilog/vpi/
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 5496d 00h /minsoc/tags/release-0.9/bench/verilog/vpi/

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