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[/] [minsoc/] [tags/] [release-0.9/] [rtl/] [verilog/] [minsoc_defines.v] - Rev 106

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42 Tagging release 0.9 of MinSoC. rfajardo 4088d 22h /minsoc/tags/release-0.9/rtl/verilog/minsoc_defines.v
20 minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.

minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.

Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too.
rfajardo 4506d 22h /minsoc/tags/release-0.9/rtl/verilog/minsoc_defines.v
7 Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o.
rfajardo 4617d 20h /minsoc/tags/release-0.9/rtl/verilog/minsoc_defines.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4632d 00h /minsoc/tags/release-0.9/rtl/verilog/minsoc_defines.v

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