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[/] [minsoc/] [tags/] [release-1.0/] [prj/] - Rev 104

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Rev Log message Author Age Path
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4579d 09h /minsoc/tags/release-1.0/prj/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4616d 11h /minsoc/tags/release-1.0/prj/
96 Some files needed for Altera synthesis javieralso 4616d 22h /minsoc/tags/release-1.0/prj/
95 Makefile for Altera FPGAs fixed javieralso 4618d 01h /minsoc/tags/release-1.0/prj/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4620d 10h /minsoc/tags/release-1.0/prj/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4620d 12h /minsoc/tags/release-1.0/prj/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4621d 11h /minsoc/tags/release-1.0/prj/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4622d 03h /minsoc/tags/release-1.0/prj/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4622d 03h /minsoc/tags/release-1.0/prj/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4622d 03h /minsoc/tags/release-1.0/prj/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4622d 04h /minsoc/tags/release-1.0/prj/

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