| Rev |
Log message |
Author |
Age |
Path |
| 151 |
Creating tag release-1.0 from revision 150 of branches/rc-1.0. |
rfajardo |
4757d 12h |
/minsoc/tags/release-1.0/prj/ |
| 133 |
Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.
Applying Rubén Diez patch to avoid warnings on firmware load for simulation. |
rfajardo |
4778d 13h |
/minsoc/branches/rc-1.0/prj/ |
| 131 |
Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail. |
rfajardo |
4782d 09h |
/minsoc/branches/rc-1.0/prj/ |
| 128 |
Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. |
rfajardo |
4782d 23h |
/minsoc/branches/rc-1.0/prj/ |
| 120 |
ethmac.prj: a file was missing |
rfajardo |
4789d 06h |
/minsoc/branches/rc-1.0/prj/ |
| 113 |
minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error
spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated
prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files |
rfajardo |
4789d 09h |
/minsoc/branches/rc-1.0/prj/ |
| 110 |
Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure
-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0
-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.
-prj/src: or1200_top.prj downdated to definition of or1200_v1 |
rfajardo |
4790d 02h |
/minsoc/branches/rc-1.0/prj/ |
| 109 |
Creating a branche for release candidate 1.0. |
rfajardo |
4790d 03h |
/minsoc/branches/rc-1.0/prj/ |
| 108 |
Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.
Icarus Verilog and Altera synthesis are working as well. Job done! |
rfajardo |
4790d 06h |
/minsoc/trunk/prj/ |
| 107 |
Adding setup batch script for Altera synthesis on Windows.
prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.
Maybe the other scripts have to be updated too. This will be checked soon. |
rfajardo |
4790d 09h |
/minsoc/trunk/prj/ |
| 104 |
Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools) |
rfajardo |
4797d 13h |
/minsoc/trunk/prj/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4834d 14h |
/minsoc/trunk/prj/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4835d 01h |
/minsoc/trunk/prj/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4836d 04h |
/minsoc/trunk/prj/ |
| 94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
4838d 13h |
/minsoc/trunk/prj/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4838d 16h |
/minsoc/trunk/prj/ |
| 91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
4839d 14h |
/minsoc/trunk/prj/ |
| 90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
4840d 06h |
/minsoc/trunk/prj/ |
| 89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
4840d 06h |
/minsoc/trunk/prj/ |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4840d 06h |
/minsoc/trunk/prj/ |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4840d 08h |
/minsoc/trunk/prj/ |
