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[/] [minsoc/] [tags/] [release-1.0/] [prj/] - Rev 97

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97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4629d 10h /minsoc/tags/release-1.0/prj/
96 Some files needed for Altera synthesis javieralso 4629d 21h /minsoc/tags/release-1.0/prj/
95 Makefile for Altera FPGAs fixed javieralso 4631d 00h /minsoc/tags/release-1.0/prj/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4633d 09h /minsoc/tags/release-1.0/prj/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4633d 12h /minsoc/tags/release-1.0/prj/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4634d 10h /minsoc/tags/release-1.0/prj/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4635d 02h /minsoc/tags/release-1.0/prj/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4635d 02h /minsoc/tags/release-1.0/prj/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4635d 02h /minsoc/tags/release-1.0/prj/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4635d 04h /minsoc/tags/release-1.0/prj/

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