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108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!
rfajardo 4623d 04h /minsoc/trunk/
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.
rfajardo 4623d 07h /minsoc/trunk/
106 Installation script was checking the ENV variable before setting it. rfajardo 4623d 10h /minsoc/trunk/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 4623d 12h /minsoc/trunk/
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 4630d 11h /minsoc/trunk/
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 4633d 02h /minsoc/trunk/
102 GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. rfajardo 4633d 02h /minsoc/trunk/
101 Documentation, wiki's address updated. rfajardo 4658d 14h /minsoc/trunk/
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 4667d 12h /minsoc/trunk/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4667d 12h /minsoc/trunk/
98 Removing deprecated minsoc_top.qsf file. rfajardo 4667d 12h /minsoc/trunk/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4667d 12h /minsoc/trunk/
96 Some files needed for Altera synthesis javieralso 4667d 23h /minsoc/trunk/
95 Makefile for Altera FPGAs fixed javieralso 4669d 02h /minsoc/trunk/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4671d 11h /minsoc/trunk/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4671d 14h /minsoc/trunk/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4672d 12h /minsoc/trunk/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4672d 12h /minsoc/trunk/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4673d 04h /minsoc/trunk/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4673d 04h /minsoc/trunk/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4673d 04h /minsoc/trunk/
87 Synchronizing scripts to behave exactly the same. rfajardo 4673d 05h /minsoc/trunk/
86 Updating configure script messages. rfajardo 4673d 06h /minsoc/trunk/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4673d 06h /minsoc/trunk/
84 syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v
rfajardo 4674d 06h /minsoc/trunk/
83 minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. rfajardo 4685d 12h /minsoc/trunk/
82 minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. rfajardo 4688d 11h /minsoc/trunk/
81 Installation script complete, nice text feedback, output logs and better execution order. rfajardo 4688d 22h /minsoc/trunk/
80 Establishing a better Makefile system for firmwares. rfajardo 4691d 10h /minsoc/trunk/
79 minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated
rfajardo 4692d 03h /minsoc/trunk/

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