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97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4614d 21h /minsoc/trunk
96 Some files needed for Altera synthesis javieralso 4615d 07h /minsoc/trunk
95 Makefile for Altera FPGAs fixed javieralso 4616d 10h /minsoc/trunk
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4618d 19h /minsoc/trunk
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4618d 22h /minsoc/trunk
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4619d 20h /minsoc/trunk
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4619d 21h /minsoc/trunk
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4620d 12h /minsoc/trunk
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4620d 12h /minsoc/trunk
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4620d 13h /minsoc/trunk

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