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160 Typo in minsoc-install.sh script. Adv_jtag_bridge was not configuring correctly. rfajardo 4543d 02h /minsoc/trunk/
159 Updated constraint file for de2_115 board. (Richard Hasha) rfajardo 4543d 03h /minsoc/trunk/
158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
rfajardo 4544d 19h /minsoc/trunk/
157 Removed obsolete file; the changes in this version have been merged into
the mainline advanced debug system version 3.0 and higher.
nyawn 4550d 14h /minsoc/trunk/
156 Added hardware watchpoint indicators to debug unit break input, to allow
the debugger to break when a hardware watchpoint is triggered.
nyawn 4550d 14h /minsoc/trunk/
155 Decreased wait time, for faster simulations. nyawn 4550d 14h /minsoc/trunk/
154 Modified to use the new autotools support in the advanced debug system v3.0. nyawn 4550d 14h /minsoc/trunk/
149 Merging differences of release candidate 1.0 revision 140:148 with trunk. rfajardo 4583d 04h /minsoc/trunk/
144 Updating configure scripts. Calling make into the right directories now. rfajardo 4589d 03h /minsoc/trunk/
142 Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.
rfajardo 4589d 03h /minsoc/trunk/
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 4589d 03h /minsoc/trunk/
135 Installation on Ubuntu-11.10 has shown that package texinfo is required to compiled GDB. This package installs the binary makeinfo. rfajardo 4596d 23h /minsoc/trunk/
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!
rfajardo 4615d 21h /minsoc/trunk/
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.
rfajardo 4616d 00h /minsoc/trunk/
106 Installation script was checking the ENV variable before setting it. rfajardo 4616d 03h /minsoc/trunk/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 4616d 05h /minsoc/trunk/
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 4623d 04h /minsoc/trunk/
103 But the file is called gdb-6.8a.tar.bz2, so tar must be run on that name. rfajardo 4625d 19h /minsoc/trunk/
102 GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. rfajardo 4625d 19h /minsoc/trunk/
101 Documentation, wiki's address updated. rfajardo 4651d 07h /minsoc/trunk/
100 syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. rfajardo 4660d 05h /minsoc/trunk/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4660d 05h /minsoc/trunk/
98 Removing deprecated minsoc_top.qsf file. rfajardo 4660d 05h /minsoc/trunk/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4660d 05h /minsoc/trunk/
96 Some files needed for Altera synthesis javieralso 4660d 16h /minsoc/trunk/
95 Makefile for Altera FPGAs fixed javieralso 4661d 19h /minsoc/trunk/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4664d 04h /minsoc/trunk/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4664d 07h /minsoc/trunk/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4665d 05h /minsoc/trunk/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4665d 05h /minsoc/trunk/

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