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Rev Log message Author Age Path
149 Merging differences of release candidate 1.0 revision 140:148 with trunk. rfajardo 3447d 03h /minsoc/trunk/backend/
144 Updating configure scripts. Calling make into the right directories now. rfajardo 3453d 02h /minsoc/trunk/backend/
142 Updating
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.
rfajardo 3453d 02h /minsoc/trunk/backend/
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 3453d 02h /minsoc/trunk/backend/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3480d 04h /minsoc/trunk/backend/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3524d 03h /minsoc/trunk/backend/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3524d 04h /minsoc/trunk/backend/
96 Some files needed for Altera synthesis javieralso 3524d 15h /minsoc/trunk/backend/
95 Makefile for Altera FPGAs fixed javieralso 3525d 18h /minsoc/trunk/backend/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3528d 05h /minsoc/trunk/backend/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3529d 03h /minsoc/trunk/backend/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3529d 20h /minsoc/trunk/backend/
87 Synchronizing scripts to behave exactly the same. rfajardo 3529d 21h /minsoc/trunk/backend/
86 Updating configure script messages. rfajardo 3529d 21h /minsoc/trunk/backend/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3529d 21h /minsoc/trunk/backend/
80 Establishing a better Makefile system for firmwares. rfajardo 3548d 02h /minsoc/trunk/backend/
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, has to be changed:
-pli ../../bench/verilog/vpi/
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3649d 03h /minsoc/trunk/backend/
69 backend update:
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/ now references to inside backend.

-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 3653d 19h /minsoc/trunk/backend/
68 Still one configuration mismatch on minsoc_defines.v:
-orp.ld is defined accordingly
rfajardo 3655d 22h /minsoc/trunk/backend/
67 Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the STARTUP module.

This module is not enabled under the respective minsoc_defines.v. Thus, its pins had to be commented out.
rfajardo 3655d 23h /minsoc/trunk/backend/

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