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158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
rfajardo 3251d 00h /minsoc/trunk/backend/
149 Merging differences of release candidate 1.0 revision 140:148 with trunk. rfajardo 3289d 09h /minsoc/trunk/backend/
144 Updating configure scripts. Calling make into the right directories now. rfajardo 3295d 08h /minsoc/trunk/backend/
142 Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.
rfajardo 3295d 09h /minsoc/trunk/backend/
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 3295d 09h /minsoc/trunk/backend/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 3322d 10h /minsoc/trunk/backend/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 3366d 10h /minsoc/trunk/backend/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3366d 11h /minsoc/trunk/backend/
96 Some files needed for Altera synthesis javieralso 3366d 21h /minsoc/trunk/backend/
95 Makefile for Altera FPGAs fixed javieralso 3368d 00h /minsoc/trunk/backend/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3370d 12h /minsoc/trunk/backend/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 3371d 10h /minsoc/trunk/backend/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3372d 03h /minsoc/trunk/backend/
87 Synchronizing scripts to behave exactly the same. rfajardo 3372d 04h /minsoc/trunk/backend/
86 Updating configure script messages. rfajardo 3372d 04h /minsoc/trunk/backend/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3372d 04h /minsoc/trunk/backend/
80 Establishing a better Makefile system for firmwares. rfajardo 3390d 08h /minsoc/trunk/backend/
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3491d 09h /minsoc/trunk/backend/
69 backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.

backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet.
rfajardo 3496d 01h /minsoc/trunk/backend/
68 Still one configuration mismatch on minsoc_defines.v:
-MEMORY_ADR_WIDTH now 15
-orp.ld is defined accordingly
rfajardo 3498d 05h /minsoc/trunk/backend/
67 Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the STARTUP module.

This module is not enabled under the respective minsoc_defines.v. Thus, its pins had to be commented out.
rfajardo 3498d 05h /minsoc/trunk/backend/
66 spartan3e_starter_kit requires special configuration of or1200_r3.

For that, configure script was specially adapted and that is reported on script execution.

For release-1.0 of MinSoC this should not be required, because or1200_r1 already has the
required configuration.
rfajardo 3498d 06h /minsoc/trunk/backend/
65 Files missing in the last commit.
backend/std/configure
sw: eth, uart and driver Makefiles
rfajardo 3498d 07h /minsoc/trunk/backend/
64 firmware makefiles:
-every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you.
-TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually.

Makefile system for synthesis:
-the dependency for every implementation step has been checked and is working fine.
-Makefile plus support files have been moved to minsoc/syn/src
-make usage is still under syn through files generated by backend bashscripts
Backend:
-files under backend are target specific files used for the system to work
-firmware compilation
-system simulation
-system implementation
-This directory is populated by visiting one of its subdirectories and typing ./configure

backend/spartan3a_dsp_kit:
-working on FPGA

backend/spartan3e_starter_kit:
-has to be tested

backend/ml509:
-missing files have to be copied and adapted, configure script has to be copied and adapted

backend/std:
-include files necessary for firmware compilation and system configuration
-it does not include files for synthesis and is not synthesizable
rfajardo 3498d 08h /minsoc/trunk/backend/
63 Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something. rfajardo 3502d 02h /minsoc/trunk/backend/
40 Commiting a contributions directory, which has raw contributions of users. These contributions still have to be adapted to the system in order to work well. However, some users are certainly able to work with these versions.

FAQ: -added new idea to circumvent onboard DLC9 cable problem for adv_jtag_bridge
INSTALL: -gives a hint on how to install the system for Windows
HOWTO: -explains what a ucf file is and how to create it

backend: now we have the first contribution of a ucf file for the ML509 board (thanks to Matthew Hick)

Documentation: THESIS.txt explains to users, willing to tweak/understand the inner behavior of the OR1200 implementation of OpenRISC, what to read in order to get this information.
rfajardo 3553d 04h /minsoc/trunk/backend/
15 Including verified pinout for external spi flash on spartan3a dsp kit to its correspondent ucf constraint file. rfajardo 4036d 02h /minsoc/trunk/backend/
13 Updating spartan3e_starter_kit.ucf so that it does not deliver errors on mapping. Moreover it has been changed to off the shelf only have uart support. Ethernet support and generic JTAG can be added by uncommenting the corresponding lines. rfajardo 4045d 09h /minsoc/trunk/backend/
12 1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.
rfajardo 4048d 01h /minsoc/trunk/backend/
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4090d 08h /minsoc/trunk/backend/

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