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165 Board contribution: nexys2_1200 (Thanks to Johan Granath)

spartan3e_starter_kit_eth/minsoc_bench_defines.v: deprecated definition updated
rfajardo 2784d 06h /minsoc/trunk/backend/
159 Updated constraint file for de2_115 board. (Richard Hasha) rfajardo 2874d 04h /minsoc/trunk/backend/
158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
rfajardo 2875d 20h /minsoc/trunk/backend/
149 Merging differences of release candidate 1.0 revision 140:148 with trunk. rfajardo 2914d 06h /minsoc/trunk/backend/
144 Updating configure scripts. Calling make into the right directories now. rfajardo 2920d 05h /minsoc/trunk/backend/
142 Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.
rfajardo 2920d 05h /minsoc/trunk/backend/
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 2920d 05h /minsoc/trunk/backend/
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 2947d 07h /minsoc/trunk/backend/
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 2991d 06h /minsoc/trunk/backend/
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 2991d 07h /minsoc/trunk/backend/
96 Some files needed for Altera synthesis javieralso 2991d 18h /minsoc/trunk/backend/
95 Makefile for Altera FPGAs fixed javieralso 2992d 21h /minsoc/trunk/backend/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 2995d 08h /minsoc/trunk/backend/
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 2996d 06h /minsoc/trunk/backend/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 2996d 23h /minsoc/trunk/backend/
87 Synchronizing scripts to behave exactly the same. rfajardo 2997d 00h /minsoc/trunk/backend/
86 Updating configure script messages. rfajardo 2997d 00h /minsoc/trunk/backend/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 2997d 00h /minsoc/trunk/backend/
80 Establishing a better Makefile system for firmwares. rfajardo 3015d 05h /minsoc/trunk/backend/
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
rfajardo 3116d 06h /minsoc/trunk/backend/

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