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[/] [minsoc/] [trunk/] [backend/] [spartan3e_starter_kit_eth] - Rev 92

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92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4621d 03h /minsoc/trunk/backend/spartan3e_starter_kit_eth
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4621d 19h /minsoc/trunk/backend/spartan3e_starter_kit_eth
87 Synchronizing scripts to behave exactly the same. rfajardo 4621d 20h /minsoc/trunk/backend/spartan3e_starter_kit_eth
86 Updating configure script messages. rfajardo 4621d 20h /minsoc/trunk/backend/spartan3e_starter_kit_eth
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4621d 21h /minsoc/trunk/backend/spartan3e_starter_kit_eth
80 Establishing a better Makefile system for firmwares. rfajardo 4640d 01h /minsoc/trunk/backend/spartan3e_starter_kit_eth
70 Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

Removing timescale definition of minsoc_bench_defines.v files.

Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
-pli ../../bench/verilog/vpi/jp-io-vpi.so
to:
-pli ../../bench/verilog/vpi/jp-io-vpi.dll

These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.		 rfajardo 4741d 02h /minsoc/trunk/backend/spartan3e_starter_kit_eth
69 backend update:
-minsoc_bench_defines.v
-gcc-opt.mk
Both files should now be under minsoc/backend to proper system functionality.
backend subdirectories have been given those files. Configure script updated accordingly.

They are searched there from system scripts and Makefiles.
-sim/bin/minsoc_verilog_files.txt has the files for Icarus Verilog, minsoc_bench_defines.v is now referenced from backend directory.
-sw/support/Makefile.inc now references to gcc-opt.mk inside backend.

backend/spartan3e_starter_kit_eth:
-It is the system configuration for Spartan 3E Starter Kit with Ethernet.		 rfajardo 4745d 18h /minsoc/trunk/backend/spartan3e_starter_kit_eth

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