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[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_memory_model.v] - Rev 60

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60 Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.

minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition.
rfajardo 3121d 12h /minsoc/trunk/bench/verilog/minsoc_memory_model.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 3708d 23h /minsoc/trunk/bench/verilog/minsoc_memory_model.v

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