Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [bench/] [verilog/] [sim_lib/] [fpga_memory_primitives.v] - Rev 17


Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
17 Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.

send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)

If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.
rfajardo 4030d 20h /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v
10 Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v.

With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers.

minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary.
rfajardo 4069d 20h /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v

powered by: WebSVN 2.1.0

© copyright 1999-2020, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.