URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [prj/] - Rev 100

Rev	Log message	Author	Age	Path
97	As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board.	rfajardo	4609d 18h	/minsoc/trunk/prj/
96	Some files needed for Altera synthesis	javieralso	4610d 05h	/minsoc/trunk/prj/
95	Makefile for Altera FPGAs fixed	javieralso	4611d 08h	/minsoc/trunk/prj/
94	Fix bug in minsoc_top.prj for Altera synthesis	javieralso	4613d 16h	/minsoc/trunk/prj/
93	Support for Altera synthesis. It needs some tune, but it works fine	javieralso	4613d 19h	/minsoc/trunk/prj/
91	prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found.	rfajardo	4614d 18h	/minsoc/trunk/prj/
90	After minsoc_top.prj update, make regenerated src and xst files.	rfajardo	4615d 09h	/minsoc/trunk/prj/
89	minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now.	rfajardo	4615d 10h	/minsoc/trunk/prj/
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4615d 10h	/minsoc/trunk/prj/
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4615d 11h	/minsoc/trunk/prj/