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[/] [minsoc/] [trunk/] [prj/] - Rev 99

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Rev Log message Author Age Path
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 3614d 07h /minsoc/trunk/prj/
96 Some files needed for Altera synthesis javieralso 3614d 18h /minsoc/trunk/prj/
95 Makefile for Altera FPGAs fixed javieralso 3615d 21h /minsoc/trunk/prj/
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 3618d 06h /minsoc/trunk/prj/
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 3618d 09h /minsoc/trunk/prj/
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3619d 08h /minsoc/trunk/prj/
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 3619d 23h /minsoc/trunk/prj/
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 3619d 23h /minsoc/trunk/prj/
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3619d 23h /minsoc/trunk/prj/
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3620d 01h /minsoc/trunk/prj/

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