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[/] [minsoc/] [trunk/] [prj/] [Makefile] - Rev 141

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141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 2920d 21h /minsoc/trunk/prj/Makefile
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 2954d 21h /minsoc/trunk/prj/Makefile
96 Some files needed for Altera synthesis javieralso 2992d 09h /minsoc/trunk/prj/Makefile
95 Makefile for Altera FPGAs fixed javieralso 2993d 12h /minsoc/trunk/prj/Makefile
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 2997d 14h /minsoc/trunk/prj/Makefile
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 2997d 16h /minsoc/trunk/prj/Makefile

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