URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [prj/] [altera/] - Rev 117

Rev	Log message	Author	Age	Path
97	As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board.	rfajardo	4615d 09h	/minsoc/trunk/prj/altera/
96	Some files needed for Altera synthesis	javieralso	4615d 20h	/minsoc/trunk/prj/altera/
95	Makefile for Altera FPGAs fixed	javieralso	4616d 23h	/minsoc/trunk/prj/altera/
94	Fix bug in minsoc_top.prj for Altera synthesis	javieralso	4619d 07h	/minsoc/trunk/prj/altera/
93	Support for Altera synthesis. It needs some tune, but it works fine	javieralso	4619d 10h	/minsoc/trunk/prj/altera/
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4621d 02h	/minsoc/trunk/prj/altera/