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[/] [minsoc/] [trunk/] [prj/] [scripts/] [simverilog.sh] - Rev 104

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104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 3184d 00h /minsoc/trunk/prj/scripts/simverilog.sh
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 3226d 01h /minsoc/trunk/prj/scripts/simprj.sh
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 3226d 17h /minsoc/trunk/prj/scripts/simprj.sh
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 3226d 19h /minsoc/trunk/prj/scripts/simprj.sh

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