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[/] [minsoc/] [trunk/] [prj] - Rev 141

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141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 4591d 13h /minsoc/trunk/prj
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!
rfajardo 4618d 07h /minsoc/trunk/prj
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.
rfajardo 4618d 10h /minsoc/trunk/prj
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)
rfajardo 4625d 13h /minsoc/trunk/prj
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4662d 15h /minsoc/trunk/prj
96 Some files needed for Altera synthesis javieralso 4663d 02h /minsoc/trunk/prj
95 Makefile for Altera FPGAs fixed javieralso 4664d 05h /minsoc/trunk/prj
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4666d 14h /minsoc/trunk/prj
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4666d 16h /minsoc/trunk/prj
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4667d 15h /minsoc/trunk/prj
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4668d 07h /minsoc/trunk/prj
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4668d 07h /minsoc/trunk/prj
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4668d 07h /minsoc/trunk/prj
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4668d 08h /minsoc/trunk/prj

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