URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [prj] - Rev 97

Rev	Log message	Author	Age	Path
97	As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board.	rfajardo	4616d 14h	/minsoc/trunk/prj
96	Some files needed for Altera synthesis	javieralso	4617d 01h	/minsoc/trunk/prj
95	Makefile for Altera FPGAs fixed	javieralso	4618d 04h	/minsoc/trunk/prj
94	Fix bug in minsoc_top.prj for Altera synthesis	javieralso	4620d 13h	/minsoc/trunk/prj
93	Support for Altera synthesis. It needs some tune, but it works fine	javieralso	4620d 16h	/minsoc/trunk/prj
91	prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found.	rfajardo	4621d 14h	/minsoc/trunk/prj
90	After minsoc_top.prj update, make regenerated src and xst files.	rfajardo	4622d 06h	/minsoc/trunk/prj
89	minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now.	rfajardo	4622d 06h	/minsoc/trunk/prj
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4622d 06h	/minsoc/trunk/prj
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4622d 08h	/minsoc/trunk/prj