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[/] [minsoc/] [trunk/] [rtl/] - Rev 25

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20 minsoc_defines.v had a semicolon at the end of the two reset polarity definitions.

minsoc_top had a signal array for two different signals which was for backward compatibility. The compatible debugging module is so old that there is no reason for keeping it.

Documentation has been updated to better explain how to use the definitions files, minsoc_defines.v and or1200_defines.v. An example for Altera devices has been added too.
rfajardo 3927d 10h /minsoc/trunk/rtl/
17 Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.

send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)

If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.
rfajardo 3992d 09h /minsoc/trunk/rtl/
16 Further initialization improvement of non-used signals, setting interrupt signals to 0 if module is not used. rfajardo 3997d 13h /minsoc/trunk/rtl/
14 Wishbone error signal of Ethernet core was not tied to ground if Ethernet was disabled. Solved now. rfajardo 4006d 14h /minsoc/trunk/rtl/
12 1) spi_top.v:
-TX_NEGEDGE bug reported and recommended solution by Blaise Gassend. (Thank you)
2) minsoc howto extended to:
-synthesis of minsoc for Spartan3E Starter Kit with Ethernet
3) spartan3e_starter_kit.ucf changed:
-it had problems regarding pin definitions and IO logic types for mapping and place&route. Working flawless now.
rfajardo 4010d 05h /minsoc/trunk/rtl/
7 Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o.
rfajardo 4038d 08h /minsoc/trunk/rtl/
6 No implementation relevant changes.

Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.

Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v.
rfajardo 4042d 14h /minsoc/trunk/rtl/
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4052d 12h /minsoc/trunk/rtl/

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