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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [altera_pll.v] - Rev 63

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63 Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something. rfajardo 4080d 02h /minsoc/trunk/rtl/verilog/altera_pll.v
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 4080d 09h /minsoc/trunk/rtl/verilog/altera_pll.v
56 Macros for all Altera family devices and pll instantiation javieralso 4087d 20h /minsoc/trunk/rtl/verilog/minsoc_pll.v
52 Altera ALTPLL Megafunction Instantiation javieralso 4097d 22h /minsoc/trunk/rtl/verilog/minsoc_pll.v

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