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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [altera_pll.v] - Rev 62

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62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 3389d 05h /minsoc/trunk/rtl/verilog/altera_pll.v
56 Macros for all Altera family devices and pll instantiation javieralso 3396d 17h /minsoc/trunk/rtl/verilog/minsoc_pll.v
52 Altera ALTPLL Megafunction Instantiation javieralso 3406d 19h /minsoc/trunk/rtl/verilog/minsoc_pll.v

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