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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Rev 16

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16 Further initialization improvement of non-used signals, setting interrupt signals to 0 if module is not used. rfajardo 4030d 13h /minsoc/trunk/rtl/verilog/minsoc_top.v
14 Wishbone error signal of Ethernet core was not tied to ground if Ethernet was disabled. Solved now. rfajardo 4039d 14h /minsoc/trunk/rtl/verilog/minsoc_top.v
7 Some changes:
-wb_cabs removed from minsoc_top.v and minsoc_tc_top.v
-added reset polarity control to minsoc_defines.v through:
-POSITIVE_RESET
-NEGATIVE_RESET
-minsoc_onchip_ram_top.v does not use
minsoc_onchip_ram.v oe signals (output enable) anymore,
which are implemented as tristate buffers. Now
minsoc_onchip_ram_top.v has a generated MUX, which
has an arbitrary number of inputs and 1 output.
Input are the internal output of the onchip_rams,
output the wb_dat_o.
rfajardo 4071d 08h /minsoc/trunk/rtl/verilog/minsoc_top.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 4085d 12h /minsoc/trunk/rtl/verilog/minsoc_top.v

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