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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_xilinx_internal_jtag.v] - Rev 175

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175 Too many `endifs added to minsoc_xilinx_internal_jtag.v in revision 174. Ronan reported it and one `endif has been removed. Thanks for that Ronan. rfajardo 2319d 15h /minsoc/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v
173 Jay Aurabind's contribution of a port to the Nexys 3 board from Digilent. Thanks!! rfajardo 2354d 19h /minsoc/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit
rfajardo 3651d 22h /minsoc/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v

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