OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [xilinx_dcm.v] - Rev 173

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
173 Jay Aurabind's contribution of a port to the Nexys 3 board from Digilent. Thanks!! rfajardo 2356d 08h /minsoc/trunk/rtl/verilog/xilinx_dcm.v
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 2935d 06h /minsoc/trunk/rtl/verilog/xilinx_dcm.v
62 Wrapping different family modules of same manufacturer in a single module.

minsoc_clock_manager.v: uses fpga manufacturer wrappers

xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

altera_pll.v: selects between different Altera FPGA families and implements the module
rfajardo 3065d 12h /minsoc/trunk/rtl/verilog/xilinx_dcm.v

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.