| Rev |
Log message |
Author |
Age |
Path |
| 63 |
Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something. |
rfajardo |
4739d 04h |
/minsoc/trunk |
| 62 |
Wrapping different family modules of same manufacturer in a single module.
minsoc_clock_manager.v: uses fpga manufacturer wrappers
xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module
altera_pll.v: selects between different Altera FPGA families and implements the module |
rfajardo |
4739d 11h |
/minsoc/trunk |
| 61 |
Removing supposely defined external function, which don't exist anymore. |
rfajardo |
4739d 12h |
/minsoc/trunk |
| 60 |
Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.
minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition. |
rfajardo |
4739d 23h |
/minsoc/trunk |
| 59 |
undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of minsoc_defines.v. Instead, the testbench now works with the right reset level to avoid the implementation ordering problem. |
rfajardo |
4740d 00h |
/minsoc/trunk |
| 58 |
Standard definitions depended on implementation order. Now, this should be solved.
minsoc_bench_defines.v: when setting reset to be positive (`define POSITIVE_RESET), NEGATIVE_RESET is undefined. This override the implementation order, so that independent of it, POSITIVE_RESET will be used.
minsoc_defines.v: when setting GENERIC_FPGA, FPGA_TAP and FPGA_CLOCK_DIVISION are undefined. This way, even if FPGA_TAP would come prior to GENERIC_TAP on the correspondent implementation, GENERIC_TAP would still be selected.
IMPORTANT: GENERIC_MEMORY must still be implemented first on minsoc_onchip_ram.v, because FPGA's memory is automatically selected from other definitions and cannot be undefined a priori. Since some other memory types can be selected, there is no trivial solution. However, this shouldn't be a big problem, since the beginning of this file will probably not be modified. |
rfajardo |
4740d 00h |
/minsoc/trunk |
| 57 |
If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.
Some updated to comments.
CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.
Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected. |
rfajardo |
4740d 00h |
/minsoc/trunk |
| 56 |
Macros for all Altera family devices and pll instantiation |
javieralso |
4746d 23h |
/minsoc/trunk |
| 55 |
Adjusting Makefiles to compile correctly with new firmware updates.
1) except.o not included into libsupport.a.
2) libsupport.a linked to except.o, now in correct order: ld libsupport.a except.o -o executable (not the other way around)
3) int.c was not being compiled because of a #ifdef which is not set anywhere |
rfajardo |
4748d 07h |
/minsoc/trunk |
| 54 |
Moving spr_defs.h to or1200.h |
ConX. |
4748d 09h |
/minsoc/trunk |
| 53 |
Indentation, deleting redundant files and adding externals |
ConX. |
4748d 10h |
/minsoc/trunk |
| 52 |
Altera ALTPLL Megafunction Instantiation |
javieralso |
4757d 01h |
/minsoc/trunk |
| 51 |
sw/support/uart.c: Changing the order of writes to the Divisor Latch of UART. (Thanks Ramkumar) |
rfajardo |
4763d 13h |
/minsoc/trunk |
| 50 |
Removing unused firmware files, respective to or1ksim actually.
Removing the inclusion of the removed file mc.h in reset.S, probably required by or1ksim at some point.
Reworked except.S to use a macro instead of repeating the same procedure 16 times or so. Explanation added to the macro as a leading comment. |
rfajardo |
4775d 10h |
/minsoc/trunk |
| 49 |
Language correction for README.txt. |
rfajardo |
4777d 07h |
/minsoc/trunk |
| 48 |
Clear some old docs that are already ported to MinSOC's Wiki |
ConX. |
4777d 08h |
/minsoc/trunk |
| 47 |
Firmware updated to work with gcc-4.5. It is actually working just fine and gcc-4.5 assembly code seems a lot cleaner.
I noticed that by increasing the free stack space for the interrupt handler by 130 made the resulting firmware not work. I assume it is because 130 is not aligned 130%4 = 2 and the stack simply does not work then. Instead I'm freeing the previous 116 plus 128 (for 32 registers as mentioned by Jeremy) and it works. |
rfajardo |
4778d 07h |
/minsoc/trunk |
| 46 |
Including an explanation of what has to be updated on gpio to port it smoothly to minsoc. |
rfajardo |
4778d 11h |
/minsoc/trunk |
| 45 |
A more stable version |
ConX. |
4779d 03h |
/minsoc/trunk |
| 44 |
Fixing some bugs. But it still works only in Debian/Ubuntu |
ConX. |
4779d 04h |
/minsoc/trunk |
