URL https://opencores.org/ocsvn/mips32r1/mips32r1/trunk

Subversion Repositories mips32r1

[/] [mips32r1/] [trunk/] [Hardware/] [MIPS32_Standalone/] - Rev 12

Rev	Log message	Author	Age	Path
12	Updated SoC bit file with hardware divider. Changed SoC frequency to a more conservative 33/66MHz clock. SoC BRAM cores must now be generated by the user. Added a README to the standalone processor directory.	ayersg	4189d 06h	/mips32r1/trunk/Hardware/MIPS32_Standalone/
10	Added hardware divide support. Thanks to Neil Russell for contributing the divide module.	ayersg	4196d 13h	/mips32r1/trunk/Hardware/MIPS32_Standalone/
9	Minor code cleanup, changed default BE bit in CP0.	ayersg	4196d 13h	/mips32r1/trunk/Hardware/MIPS32_Standalone/
7	Corrected functionality of Jal.	ayersg	4206d 08h	/mips32r1/trunk/Hardware/MIPS32_Standalone/
3	Made whitespace consistent in all Verilog files.	ayersg	4223d 13h	/mips32r1/trunk/Hardware/MIPS32_Standalone/
2	Initial release	ayersg	4224d 00h	/mips32r1/trunk/Hardware/MIPS32_Standalone/