URL https://opencores.org/ocsvn/mips32r1/mips32r1/trunk

Subversion Repositories mips32r1

[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] - Rev 11

Rev	Log message	Author	Age	Path
11	SoC project files updated to include divide module.	ayersg	4207d 14h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/
10	Added hardware divide support. Thanks to Neil Russell for contributing the divide module.	ayersg	4207d 14h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/
9	Minor code cleanup, changed default BE bit in CP0.	ayersg	4207d 15h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/
8	Added information for regenerating the BRAM core for the SoC.	ayersg	4217d 09h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/
7	Corrected functionality of Jal.	ayersg	4217d 09h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/
6		ayersg	4231d 07h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/
5	Added a howto for getting started.	ayersg	4232d 11h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/
4	Added a howto for getting started.	ayersg	4232d 12h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/
3	Made whitespace consistent in all Verilog files.	ayersg	4234d 14h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/
2	Initial release	ayersg	4235d 01h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/