URL https://opencores.org/ocsvn/mips32r1/mips32r1/trunk

Subversion Repositories mips32r1

[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [iseconfig/] [Top.xreport] - Rev 12

Rev	Log message	Author	Age	Path
12	Updated SoC bit file with hardware divider. Changed SoC frequency to a more conservative 33/66MHz clock. SoC BRAM cores must now be generated by the user. Added a README to the standalone processor directory.	ayersg	4189d 10h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/iseconfig/Top.xreport
11	SoC project files updated to include divide module.	ayersg	4196d 16h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/iseconfig/Top.xreport
2	Initial release	ayersg	4224d 04h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/iseconfig/Top.xreport