URL https://opencores.org/ocsvn/mips32r1/mips32r1/trunk

Subversion Repositories mips32r1

[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [src/] [MIPS32/] [Hazard_Detection.v] - Rev 10

Rev	Log message	Author	Age	Path
10	Added hardware divide support. Thanks to Neil Russell for contributing the divide module.	ayersg	4205d 21h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Hazard_Detection.v
9	Minor code cleanup, changed default BE bit in CP0.	ayersg	4205d 21h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Hazard_Detection.v
7	Corrected functionality of Jal.	ayersg	4215d 16h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Hazard_Detection.v
3	Made whitespace consistent in all Verilog files.	ayersg	4232d 21h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Hazard_Detection.v
2	Initial release	ayersg	4233d 07h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Hazard_Detection.v