URL https://opencores.org/ocsvn/mips32r1/mips32r1/trunk

Subversion Repositories mips32r1

[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw] - Rev 12

Rev	Log message	Author	Age	Path
12	Updated SoC bit file with hardware divider. Changed SoC frequency to a more conservative 33/66MHz clock. SoC BRAM cores must now be generated by the user. Added a README to the standalone processor directory.	ayersg	4200d 10h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw
11	SoC project files updated to include divide module.	ayersg	4207d 16h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw
10	Added hardware divide support. Thanks to Neil Russell for contributing the divide module.	ayersg	4207d 16h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw
9	Minor code cleanup, changed default BE bit in CP0.	ayersg	4207d 17h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw
7	Corrected functionality of Jal.	ayersg	4217d 11h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw
3	Made whitespace consistent in all Verilog files.	ayersg	4234d 16h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw
2	Initial release	ayersg	4235d 03h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw