URL https://opencores.org/ocsvn/mips32r1/mips32r1/trunk

Subversion Repositories mips32r1

[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC] - Rev 12

Rev	Log message	Author	Age	Path
12	Updated SoC bit file with hardware divider. Changed SoC frequency to a more conservative 33/66MHz clock. SoC BRAM cores must now be generated by the user. Added a README to the standalone processor directory.	ayersg	4212d 04h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC
11	SoC project files updated to include divide module.	ayersg	4219d 10h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC
10	Added hardware divide support. Thanks to Neil Russell for contributing the divide module.	ayersg	4219d 11h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC
9	Minor code cleanup, changed default BE bit in CP0.	ayersg	4219d 11h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC
8	Added information for regenerating the BRAM core for the SoC.	ayersg	4229d 05h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC
7	Corrected functionality of Jal.	ayersg	4229d 06h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC
6		ayersg	4243d 04h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC
5	Added a howto for getting started.	ayersg	4244d 08h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC
4	Added a howto for getting started.	ayersg	4244d 08h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC
3	Made whitespace consistent in all Verilog files.	ayersg	4246d 11h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC
2	Initial release	ayersg	4246d 22h	/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC