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Rev Log message Author Age Path
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5464d 18h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5507d 09h /
39 bug fix. mikel262 5510d 07h /
38 Reduced processing latency of Huffman encoding mikel262 5535d 08h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5539d 12h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5541d 08h /
35 Added check for image width in testbench. mikel262 5541d 20h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5542d 04h /
33 mikel262 5542d 13h /
32 mikel262 5543d 08h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5546d 09h /
30 mikel262 5546d 22h /
29 mikel262 5547d 05h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5547d 06h /
27 mikel262 5549d 18h /
26 mikel262 5549d 19h /
25 moved from branch to trunk mikel262 5549d 19h /
24 mikel262 5549d 19h /
23 mikel262 5551d 05h /
22 Changed divider to use reciprocal lookup table. Improved Huffman processing time. BUF_FIFO almost full signal modified. mikel262 5552d 06h /

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