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Rev Log message Author Age Path
52 Redesigned BUF_FIFO.vhd to significantly reduce area utilization.
Only memory optimized version now possible.		 mikel262 5288d 18h /
51 fix in buf fifo (synthesis problem) mikel262 5292d 16h /
50 mikel262 5293d 01h /
49 Added 16 bit RGB 565 input format. mikel262 5293d 01h /
48 mikel262 5293d 02h /
47 mikel262 5293d 02h /
46 x1 mikel262 5302d 04h /
45 stall re-added mikel262 5302d 04h /
44 stall re-added mikel262 5302d 04h /
43 stall readded mikel262 5302d 04h /
42 Added backpressure/stallability of output interface. mikel262 5305d 16h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5443d 03h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5485d 18h /
39 bug fix. mikel262 5488d 16h /
38 Reduced processing latency of Huffman encoding mikel262 5513d 17h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5517d 21h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5519d 17h /
35 Added check for image width in testbench. mikel262 5520d 05h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5520d 13h /
33 mikel262 5520d 22h /
32 mikel262 5521d 17h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5524d 18h /
30 mikel262 5525d 06h /
29 mikel262 5525d 14h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5525d 14h /
27 mikel262 5528d 03h /
26 mikel262 5528d 04h /
25 moved from branch to trunk mikel262 5528d 04h /
24 mikel262 5528d 04h /
23 mikel262 5529d 14h /

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