URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 24

Rev	Log message	Author	Age	Path
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4210d 05h	/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4210d 19h	/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4215d 01h	/
1	The project and the structure was created	root	4217d 00h	/