URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 33

Rev	Log message	Author	Age	Path
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4211d 12h	/
12	updated comments, file is now completely according to design rules	JonasDC	4211d 12h	/
11	simulation output folder	JonasDC	4211d 15h	/
10	changed signal input port names to correct name	JonasDC	4211d 17h	/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4211d 17h	/
8	added descriptive comments	JonasDC	4211d 20h	/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4211d 20h	/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4211d 20h	/
5	not needed on svn, is generated by testbench	JonasDC	4211d 20h	/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4211d 22h	/