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Rev Log message Author Age Path
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4192d 23h /
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4193d 01h /
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4193d 02h /
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4193d 05h /
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4193d 06h /
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4193d 11h /
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4193d 12h /
29 added software for generation of test input for the tesbenches JonasDC 4194d 01h /
28 updated makefile for new pipeline sources JonasDC 4194d 02h /
27 test input values for multiplier_tb JonasDC 4194d 02h /
26 testbench for only the montgommery multiplier JonasDC 4194d 02h /
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4194d 02h /
24 changed names of top-level module to mod_sim_exp_core JonasDC 4197d 11h /
23 added descriptive comments JonasDC 4197d 12h /
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4200d 06h /
21 changed x_i signal to xi JonasDC 4201d 13h /
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4201d 13h /
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4206d 08h /
18 updated stages with comments and renamed some signals for consistency JonasDC 4207d 08h /
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4207d 13h /

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