| Rev |
Log message |
Author |
Age |
Path |
| 39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4192d 20h |
/ |
| 38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4193d 01h |
/ |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4196d 22h |
/ |
| 36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4197d 18h |
/ |
| 35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4197d 21h |
/ |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4197d 22h |
/ |
| 33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4198d 01h |
/ |
| 32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4198d 02h |
/ |
| 31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4198d 07h |
/ |
| 30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4198d 07h |
/ |
| 29 |
added software for generation of test input for the tesbenches |
JonasDC |
4198d 20h |
/ |
| 28 |
updated makefile for new pipeline sources |
JonasDC |
4198d 21h |
/ |
| 27 |
test input values for multiplier_tb |
JonasDC |
4198d 21h |
/ |
| 26 |
testbench for only the montgommery multiplier |
JonasDC |
4198d 21h |
/ |
| 25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4198d 21h |
/ |
| 24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4202d 06h |
/ |
| 23 |
added descriptive comments |
JonasDC |
4202d 07h |
/ |
| 22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4205d 01h |
/ |
| 21 |
changed x_i signal to xi |
JonasDC |
4206d 08h |
/ |
| 20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4206d 09h |
/ |
| 19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4211d 04h |
/ |
| 18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4212d 03h |
/ |
| 17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4212d 08h |
/ |
| 16 |
package with modified generic parameter for register_n |
JonasDC |
4212d 22h |
/ |
| 15 |
changed generic for register width from n to width for consistency |
JonasDC |
4212d 22h |
/ |
| 14 |
changed comments, file is now according to OC design rules |
JonasDC |
4212d 22h |
/ |
| 13 |
added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules |
JonasDC |
4212d 22h |
/ |
| 12 |
updated comments, file is now completely according to design rules |
JonasDC |
4212d 22h |
/ |
| 11 |
simulation output folder |
JonasDC |
4213d 00h |
/ |
| 10 |
changed signal input port names to correct name |
JonasDC |
4213d 03h |
/ |
