URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 39

Rev	Log message	Author	Age	Path
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4211d 06h	/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4212d 06h	/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4212d 11h	/
16	package with modified generic parameter for register_n	JonasDC	4213d 00h	/
15	changed generic for register width from n to width for consistency	JonasDC	4213d 00h	/
14	changed comments, file is now according to OC design rules	JonasDC	4213d 01h	/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4213d 01h	/
12	updated comments, file is now completely according to design rules	JonasDC	4213d 01h	/
11	simulation output folder	JonasDC	4213d 03h	/
10	changed signal input port names to correct name	JonasDC	4213d 06h	/