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Subversion Repositories mod_sim_exp

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Rev	Log message	Author	Age	Path
55	updated resource usage in comments	JonasDC	4095d 20h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4095d 20h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4096d 03h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4096d 03h	/
51	true dual port ram for xilinx	JonasDC	4096d 04h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4096d 04h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4107d 23h	/
48	Tag of the starting version of the project	JonasDC	4107d 23h	/
47	added documentation for the IP core.	JonasDC	4176d 04h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4176d 04h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4176d 04h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4179d 21h	/
43	made the core parameters generics	JonasDC	4179d 22h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4186d 05h	/
41	removed deprecated files from version control	JonasDC	4186d 05h	/
40	adjusted core instantiation to new core module name	JonasDC	4194d 09h	/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4194d 21h	/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4195d 02h	/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4198d 23h	/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4199d 19h	/
35	new test values, 1st exponentiation gives error on result with new pipeline commit for test purposes	JonasDC	4199d 22h	/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4199d 23h	/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4200d 02h	/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4200d 03h	/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4200d 08h	/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4200d 08h	/
29	added software for generation of test input for the tesbenches	JonasDC	4200d 22h	/
28	updated makefile for new pipeline sources	JonasDC	4200d 22h	/
27	test input values for multiplier_tb	JonasDC	4200d 22h	/
26	testbench for only the montgommery multiplier	JonasDC	4200d 22h	/

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