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Subversion Repositories mod_sim_exp

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Rev	Log message	Author	Age	Path
55	updated resource usage in comments	JonasDC	4107d 04h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4107d 05h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4107d 11h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4107d 12h	/
51	true dual port ram for xilinx	JonasDC	4107d 12h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4107d 12h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4119d 07h	/
48	Tag of the starting version of the project	JonasDC	4119d 07h	/
47	added documentation for the IP core.	JonasDC	4187d 12h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4187d 12h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4187d 12h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4191d 06h	/
43	made the core parameters generics	JonasDC	4191d 06h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4197d 14h	/
41	removed deprecated files from version control	JonasDC	4197d 14h	/
40	adjusted core instantiation to new core module name	JonasDC	4205d 18h	/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4206d 05h	/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4206d 10h	/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4210d 07h	/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4211d 04h	/

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[/] - Rev 55

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