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Rev Log message Author Age Path
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 3511d 17h /
56 this is a branch to test performance of a new style of ram JonasDC 3511d 19h /
55 updated resource usage in comments JonasDC 3512d 16h /
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 3512d 16h /
53 correctly inferred ram for altera dual port ram JonasDC 3512d 23h /
52 correct inferring of blockram, no additional resources. JonasDC 3512d 23h /
51 true dual port ram for xilinx JonasDC 3513d 00h /
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3513d 00h /
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 3524d 19h /
48 Tag of the starting version of the project JonasDC 3524d 19h /
47 added documentation for the IP core. JonasDC 3593d 00h /
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3593d 00h /
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3593d 00h /
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3596d 17h /
43 made the core parameters generics JonasDC 3596d 17h /
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3603d 01h /
41 removed deprecated files from version control JonasDC 3603d 01h /
40 adjusted core instantiation to new core module name JonasDC 3611d 05h /
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 3611d 17h /
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 3611d 22h /

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