URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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Rev	Log message	Author	Age	Path
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4087d 07h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4087d 10h	/
55	updated resource usage in comments	JonasDC	4088d 07h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4088d 07h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4088d 13h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4088d 14h	/
51	true dual port ram for xilinx	JonasDC	4088d 15h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4088d 15h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4100d 10h	/
48	Tag of the starting version of the project	JonasDC	4100d 10h	/
47	added documentation for the IP core.	JonasDC	4168d 14h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4168d 15h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4168d 15h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4172d 08h	/
43	made the core parameters generics	JonasDC	4172d 08h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4178d 16h	/
41	removed deprecated files from version control	JonasDC	4178d 16h	/
40	adjusted core instantiation to new core module name	JonasDC	4186d 20h	/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4187d 07h	/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4187d 13h	/

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Subversion Repositories mod_sim_exp

[/] - Rev 57

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